Micron Targets 42 Gb/mm2 NAND

Micron detailed its next generation of 3D NAND flash on Wednesday, projecting that the G11 architecture will double storage density compared to its current lineup. The company expects to begin high-volume production in the second half of 2027. This timeline places the launch after similar next-generation offerings from competitors Kioxia and Samsung, though Micron claims its new chips will surpass their density figures.

The density increase stems from a shift from approximately 21 Gb/mm2 in the existing G9 generation to 42 Gb/mm2 in G11 triple-level-cell form. Micron also projects a 50% improvement in input/output speeds, raising the rate from 3,600 MT/s to 5,400 MT/s. Energy efficiency is expected to improve as well, with the power required to transfer each bit dropping by more than 25%. These specifications target both conventional high-capacity solid-state drives and emerging storage solutions designed for artificial intelligence workloads.

A core technical change involves the adoption of wafer-on-wafer bonding. This method allows Micron to manufacture the NAND array and the peripheral circuitry on separate wafers using distinct processes before bonding them together. While Micron has utilized CMOS-under-array designs for several generations, bonding provides greater flexibility to optimize the memory array and logic independently. Chinese rival YMTC has already employed this bonding technique.

Scott DeBoer, Micron's president and chief technology and products officer, stated that the company waited for the technology to become cost-effective and relevant to product specifications. "This is the right timing for that technology," DeBoer said, describing G11 as the world's most advanced NAND. He confirmed the design relies on wafer-on-wafer bonding to achieve the stated performance gains.

Micron has not disclosed the exact number of active wordline layers for G11, but confirmed the design will exceed 400 layers. The company attributes the density jump to a combination of increased layer counts and an industry-leading memory cell pitch. Further technical details are expected to be released in 2027 as high-volume production approaches.

Beyond G11, Micron outlined plans to continue scaling in all three dimensions. DeBoer mentioned the development of high-mobility materials and ultra-dense cell architectures aimed at improving transistor characteristics and reducing energy consumption. "Beyond G11, we have a strong roadmap, not going to go into great detail on it today," he said. Specific architectural targets and production schedules for subsequent generations have not been disclosed.